This paper presents a novel ISFET architecture with in-pixel ADC for large-scale integration with on-chip computational capabilities. Each pixel is composed by a comparator connected to a set of memory elements, storing in-pixel each conversion. Using this sensing scheme, the entire frame is acquired and stored in one single ADC cycle, eliminating the need for global or column-level ADCs and making this architecture scalable to larger arrays without instrumentation overhead. To enable compensation of ISFET non-idealities such as trapped charge, a novel gate-bootstrapping mechanism is introduced, enhancing the ADC dynamic range without additional circuitry and accommodating an input range of 4.45 V. Fabricated in standard 180nm CMOS technology, the system is composed by a 16x16 ISFET array, a global DAC and a Digital Control Unit that enables operation and off-chip communication. This Digital ISFET Sensor (DIS) architecture represents an step forwards towards smart chemical arrays, where computational, memory and sensing elements are integrated at the pixel level to analyse the sensing information in-pixel, moving from a data-harvest approach to a information-focused strategy.