In this paper, the principle of direct tunnelling current is applied to eliminate the trapped charge in the passivation layer of CMOS ISFETs. A two-transistors frontend is implemented to achieve the most compact structure. For each ISFET the gate voltage will stabilise to a self-settled point regardless of its initial voltage (trapped charge) after reaching a balance between two tunnelling currents, from gate to source and from gate to drain. We have demonstrated the effects of different transistor sizes on this charge cancellation process. And based on above mentioned frontend, by adopting a feedback circuit to control the magnitude of the gate tunnelling current, the rate of the cancellation process can be controlled. Test results show that the total duration of the process can be manipulated in 2 orders of magnitude. In addition to that, this design essentially performs a high-pass filter with cutoff frequency tunable from 14mHz to 0.3Hz approximately.