In this paper, we describe the design of a minimalist standard cell library (inverter, NAND and D flip-flop) in a conventional 130 nm CMOS technology optimized for operation at VDD = 90 mV. The classical six-transistor CMOS Schmitt trigger was used as the basic cell of the logic family. Experimental results for a 15-stage frequency divider chain demonstrate operation at 32 kHz with a supply voltage of only 76 mV.