We propose a methodology for the simulation of electrostatic confinement wells in transistors at cryogenic temperatures. This is considered in the context of 22-nm FD-SOI transistors due to their potential in scalable quantum computing systems. To overcome thermal fluctuations and improve decoherence times in most quantum bit implementations, they must be operated at cryogenic. We review the dominant sources of electric field at these low temperatures, including material interface work function differences and trapped interface charges. Intrinsic generation and dopant ionisation are shown to be negligible at cryogenic in confinement. We propose studying cryogenic confinement wells in transistors by decoupling carrier transport generated fields.