A 12-bit, programmable hybrid ADC for CMOS image sensor is proposed in this paper. The hybrid ADC internally uses cyclic-SAR architecture and results in an area-efficient and high-speed design. To minimize the total column ADC area, the elements of cyclic ADC are reused for SAR operation. The 12-bit programmable ADC can be operated either in high-resolution mode or high-speed mode depending on the number of bits allocated per stage. The prototype CMOS image sensor is designed and fabricated in AMS 350 nm CMOS OPTO process. A three-transistor pixel architecture followed by a column parallel-readout circuit is implemented in a 9 um column pitch. A prototype 128x96 image sensor consumes 62.7 mW of power at 3.3 V power supply.