We have designed and fabricated a multi-core, multi-pairing crypto-processor on BN curve over 254bit prme field in 65nm CMOS process. We have designed optimal 2-layer sequencer for flexible operation, realizes up to 96.7% computation efficiency, with canceling data I/O overhead by double buffer architecture. Measurement results demonstrates 3.0 times faster with optimal 12-thread scheduling, and 2.9 times higher throughput and 1.7 times smaller energy consumption with 3-parallel scheduling than ever reorted. Flexible architecture enables to be utilized and accelarate the advanced crypto-algorithm such like inner product encryption and searchable encryption.