A high-speed comparator constituted by a back-gate-input latch and a pre-amplifier is proposed in this paper. Instead of using extra input transistors as in a classic StrongARM latch, the back-gate-input technique proposed in this paper obviates the need for extra input transistors in the latch stage, thus greatly reducing the parasitic capacitance and improving the comparator speed. Unlike the StrongARM latch where the amplification phase begins only after the CLK rises, the amplification phase in this paper begins before the CLK rises and replaces the reset phase, further improving the comparator speed. The pre-amplifier provides a gain of 22-dB, in order to suppress the input-referred noise and offset of the comparator. Designed in the same 22nm Silicon-on-Insulator (SOI) CMOS process for the proposed comparator and the conventional comparators, post-layout simulation results show that the performance in speed and input-referred noise are improved by 22% and 43%, respectively.