Developing machine learning (ML) accelerators in hardware involves implementing ML algorithms on chip, which are impossible to simulate using low-level commercial EDA tools. Asynchrony is a way towards significant energy-efficiency, important for artificial intelligence (AI) today. FPGA-based prototyping could help make design automation feasible, but existing FPGAs are clocked, not directly suitable for prototyping asynchronous ML hardware. This paper describes a method of prototyping asynchronous hardware designs using FPGAs and demonstrates it by prototyping asynchronous circuits implementing a novel ML algorithm, known as the Tsetlin machine. Different example systems are tackled successfully including ML circuits of up to 9513 LUTs.