This paper presents Access-Aware Per-bank DRAM Refresh, a refresh control method that mitigates the negative impacts of refreshes, and its memory controller architecture. Novel capabilities are introduced in the memory controller. An access-aware refresh control unit analyses the short-term history of memory accesses translating row activations into refresh masks that are used either to skip rows, shortening the refresh cycle, or to completely omit refresh operations. The set of DRAM commands is extended with two new per-bank refresh commands that provide the memory controller an ability to omit refreshes and context-rich fine-grained control of refresh operations.