The paper proposes a receiver frontend operating at 64Gb/s with a bandwidth of 50GHz and transimpedance gain of 70dBOhm. It consists of a burst-mode transimpedance amplifier (TIA) distributed feedback voltage amplifiers and two offset control mechanisms. By using negative and positive feedback, the gain is decoupled from bandwidth. Realized in a 65nm CMOS LPE technology, the occupied real estate on chip is 2mm2. The measurement results show operation at 64Gb/s with PAM4 signals and NRZ signals.