Spatial permutation modulation (SPM) is a new multiple-input-multiple-output (MIMO) technology for next-generation communication systems, which is an extension of spatial modulation (SM) that conveys data information at multiple time instants. By encoding the permutation of activated antennas at several time instants, the SPM system gains benefits of transmit and time diversities enabling reliable mobile communications. This study proposed a low-complexity SPM detector, called multiple-candidate-selection matching maximal ratio combining detector (MCSMMRC), for the SPM system. The MCSMMRC detector has very low complexity, fixed throughput, and scalable computing structure, which makes MCSMMD suitable for hardware implementation. This study designed and implemented the proposed MCSMMD detector by using a Xilinx Vertex-7 FPGA chip. The FPGA implementation esults showed that it achieved a maximum throughput of 538 Mbps and exhibited better normalized throughput than those of other SM-based detector chips in the literature.