This work proposes a high-speed pipelined-two-step time-to-digital converter (TDC) with a dynamic time amplifier (DTA) to improve the resolution at low power. The proposed TDC consists of a coarse TDC, a fine TDC, a DTA, and a decoder. The DTA consists of a time-to-voltage converter (TVC) and a voltage-to-time converter (TVC). It samples the residual time error as voltages held in the MOM capacitors, and discharges them to generate the amplified time difference. Thanks to the dynamic time-voltage-time conversion, the DTA achieves high linearity and power efficiency, which can be employed to build pipeline TDC architecture with high sampling frequency. Simulations show the TDC designed in 65 nm technology achieves 8-bit, 1.75 ps of time resolution at 400 MHz sampling frequency while just consuming 716 μW power, which corresponds to 18.2 fJ/Conv. FoM.