This paper presents an asynchronous 2-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). The offset mismatches among the three comparators are background calibrated by quantizing the same residue signal during the last 1-bit cycle. It eliminates the dependence on the signal distribution and utilizes the following sampling phase for the settling of the calibration voltages. An asynchronous timing sequence is also proposed to avoid an external high speed clock generator. A design example of 8-bit 500 MS/s SAR ADC in 40nm CMOS technology is presented. Simulation results show that with Nyquist input, the spurious-free-dynamic-range (SFDR) achieves 56.57 dB while the effective number of bits (ENOBs) is 7.5 bits.