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Video s3
    Details
    Poster
    Presenter(s)
    Qier Ma Headshot
    Display Name
    Qier Ma
    Affiliation
    Affiliation
    Technische Universität Dresden
    Country
    Country
    Germany
    Author(s)
    Display Name
    Qier Ma
    Affiliation
    Affiliation
    Technische Universität Dresden
    Display Name
    Liyuan Guo
    Affiliation
    Affiliation
    Technische Universität Dresden
    Affiliation
    Affiliation
    Technische Universität Dresden
    Display Name
    Christian Mayr
    Affiliation
    Affiliation
    Technische Universität Dresden
    Abstract

    This paper proposes an ultra-low-power hardware accelerator for adaptive neural signal lossless compression. It consists of second-order differential pulse code modulation (DPCM) and an adaptive encoding engine. In this work, the neural signal is first decorrelated. Then, an adaptive Golomb coding algorithm is proposed to compress data based on optimal parameters obtained from the signals in real-time. The simulation results show that the average space saving ratio (SSR) is 61.84%. The proposed design is implemented in 28nm CMOS technology and occupies an area of 792.4μm^2 and consumes 1.05μW at a frequency of 5MHz which outperforms the state-of-the-art lossless designs.

    Slides
    • Ultra-Low Power and Area-Efficient Hardware Accelerator for Adaptive Neural Signal Compression (application/pdf)