A type-II analog phase-locked loop without charge pump and analog loop filter is proposed in this paper. A novel discrete proportional-integral-derivative circuit (DPIDC) is proposed to implement phase error integration and frequency compensation with time-domain processing. A phase-to-voltage converter (PVC) with a sample-and-hold is used to convert the phase error processed by the DPIDC to a voltage that controls the voltage-controlled oscillator (VCO). Simulation results in 180nm CMOS technology show the proposed DPIDC and PVC circuits only consume 6.5-μW power at 0.6-V supply voltage. The proposed PLL settles down fast and achieves an excellent normalized reference-spur rejection better than -84.6dBc.