Details
Poster
Presenter(s)
![Junjie Gu Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/12411_0.jpg?h=2c4e73f8&itok=9F9Ok5i-)
Display Name
Junjie Gu
- Affiliation
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AffiliationFudan University
- Country
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CountryChina
Abstract
In this paper, the analysis and design of a 57-64GHz CMOS Power Amplifier is discussed. The power-combining technique and the capacitor neutralization technique are applied to boost the performance of the purposed PA. The PA is designed in 65nm bulk CMOS process to achieve a saturated output power of 19.4dBm and a peak power-added efficiency of 22%. The power amplifier consumes 300mW from a 1.2V power supply at the output-refereed 1dB compression point of 16.1dBm, and the corresponding power-added efficiency is 13.0%. The passive devices, such as the transformers, the power-combiner and the pads, are designed by Electromagnetic Field Simulation on ADS momentum.