In this paper, we have presented a current reference gener- ator circuit in 65 nm CMOS technology. By using a modified beta multiplier circuit with PTC and PMOS source follower, we achieve the relevant PVT compensation. The reference current generated in this design is 8.8 µA with supply voltage of 1.2 V giving the power consumption of 126.56 µW. Process variation in the case is 0.56% and temperature drift of 276.8 ppm/ ºC for the temperature range of 0ºC to 100ºC.