In an effort to reduce the power consumption required by artificial intelligence algorithms, many researchers are taking inspiration from biological neurons to develop spiking neural networks (SNN). The idea is to replace the currently used neural output functions by voltage or current spikes that are sparse in time. However, although possible in simulation, SNNs do not run efficiently on current hardware such as CPUs or GPUs. This work presents the foundation for the development of a neuromorphic spiking neural network processor based on the Leaky Integrate-and-Fire (LIF) neuron model. A low power digital spiking circuit is designed from an 8-bit partial magnitude comparator (PMC). The 8-bit PMC is made from modified Gate Diffusion Input (m-GDI) logic gates and achieves an average power of 4.51μW and an average delay of 80.32ps. The spiking circuit has an average power of 4.587μW and can work up to a frequency of 17.86GHz. This spiking circuit is the first step towards the realization of a large scale synchronous spiking neural network processor.