Static Random Access Memory (SRAM) is a part of physical memory which is volatile, faster and power hungry. It draws a significant amount of power in comparison to other components of a computer, which is why reducing power consumption of SRAM contributes to the reduction of power consumption of overall system. Different circuit design techniques are introduced so far, to lower the power consumption. Adiabatic is a promising circuit design technique for low power VLSI design. Primarily, adiabatic logic can be divided into two kinds; Asymptotically adiabatic logic and Quasi-adiabatic logic [1]. In this paper, adiabatic is used to mean quasi-adiabatic. The main principle of adiabatic logic is to slowing down the charging and discharging process to reduce the energy dissipation and power consumption. Adiabatic Logic is more effective for the ultra-low power applications where low power consumption is more prioritized than speed. In this paper, a SRAM cell is proposed using a novel Quasi-Adiabatic Logic which draws less power than its predecessors. Simulations are performed on Cadence Virtuoso using gpdk090.