While prototyping ASIC designs on multi-FPGA platforms, challenges like partitioning and multiplexing limited I/O cause significant delays and unpredictability in schedule. This process also requires highly skilled engineers who have deep understanding of the SoC designs. Automating this partitioning process using AI/ML techniques can potentially reduce time-to-market in addition to potential savings in engineering resources. We propose an algorithm that will automate the entire process of clustering and mapping, eliminating human intervention. We see good quality partitions with our experiments on 3 SoC designs and confirmed their feasibility by manually mapping these and checking routing feasibility.