This paper presents an integrated fractional N Phase Locked Loop (PLL) implemented in 65nm CMOS, targeting mmWave communications and RADAR applications. The IC is comprised of a PLL with integrated active loop filter, Voltage-Controlled Oscillator and auxiliary blocks, such as an auto-calibration unit, ramp generator, bandgap and lock detector. It uses an external reference frequency 40 to 320MHz and provides an output signal in the range 8.8 to 9.9 GHz with low phase noise and output power 0dBm on 50ohm. The total silicon area is 2.2x0.76mm2 and its power consumption is 270mW from a 1.8V supply.