We propose the design architecture of the LDPC encoder and decoder based on the WiMAX standard (IEEE 802.16e). The design architectures were implemented on a Kintex-7 KC705 field-programmable gate array (FPGA) kit, for a rate 1/2 WiMAX LDPC code with a code length of 2304, containing twelve layers in the parity check matrix. A new null bypassing logic for irregular LDPC decoder is proposed. The tool reported a total power of 0.677 W for encoder with a throughput of 364 Gbps. The tool reported a total power of 1.009 W for the decoder with a throughput of 0.0785 Gbps (78.5 Mbps) for five iterations. Our architecture is also amenable for constructing non-binary LDPC codes where each bit of the non-binary code is binary coded and interleaved, useful for applications in optical transmission channels. Our architecture is also scalable for a wide range of quasi-cyclic code parameters.