High-Level Synthesis (HLS) tools are an attractive option for fast prototyping and implementation of hardware accelerators performing digital signal processing algorithms such as the Fast Fourier Transform (FFT). However, the efficiency and the performance level of the generated architectures depend on the behavioral models. Moreover, Design Space Exploration features enabled by HLS tools are limited by the behavioral model parallelization features. In this paper, a generic FFT behavioral model usable within HLS tools is presented. Its parameters allow to cover a broader architectural space by taking advantage of all parallelization strategies contrary to related works. Thus, this designed model can produce low-complexity architectures up to high throughput ones as highlighted by experimental results.