We propose a new DVFS method, which alleviates the memory stall and reduce CPU power consumption utilizing a microarchitectural information. Our proposed method identifies the layer on the memory hierarchy that mainly generates the memory stall and determines the optimal frequency of CPU and memory hierarchy that achieve a system-wide power optimization, without degrading the performance. In our experiments, our proposed method improved IPC (Instruction Per Cycle) by 11%, reduced MSPC (Memory Stall Per Cycle) by 26% and reduced power consumption by 5% compared to a conventional DVFS method.