This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency divider circuit, accompanied with an accumulator that controls the division count. The circuit is capable of operating as an integer or as a fractional divider. Key topic of this paper is the merging of div-2/3 and div-3/4 circuits into a single compact circuit that solves an issue of a forbidden state in fractional-division operation. The circuit is designed with 28-nm CMOS technology and the post-layout simulations indicate an operating input frequency range of 0.3 – 5.4 GHz with 13-bit fractional frequency resolution between division ratios of 2–4. The divider occupies only 40 µm x 30 µm while consuming 2.0 mW at 5.4 GHz input frequency