Details
Poster
Presenter(s)
![Yanchi Dong Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/20371.jpg?h=d47e9e2f&itok=C9c0ZhSP)
Display Name
Yanchi Dong
- Affiliation
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AffiliationPeking University
- Country
Abstract
A 14GHz digitally controlled oscillator (DCO) is proposed for all-digital phase-locked loop (ADPLL). With a cascade differential-capacitor array, the resolution of DCO is enhanced, which leads to a decrease in quantization noise, while area cost and substrate noise are also significantly reduced. In addition, a resistor-biased DCO output buffer is used to cut down phase noise by eliminating flicker and thermal noise conventional current-mirror structure brings. The proposed DCO is designed in 14nm FinFET process, achieving a phase noise of -110dBc/Hz at 1MHz offset and a frequency resolution of 7KHz. DCO operates in a wide frequency range of 17.8%, with a 0.017 mm2 core chip area. The DCO consumes 6.3mW from a 0.8V supply voltage.