Reed-Solomon (RS) codes and their binary BCH subcodes have been traditionally used for error correction in numerous digital communication and storage systems, such as optical communications, deep-space probing, Flash memories, and magnetic storage. Variations of RS/BCH codes are also the best candidates for many emerging systems. Through nesting RS/BCH codes, the recently-developed generalized integrated interleaved (GII) codes can meet the terabit/s throughput and excellent error-correcting capability requirements of next-generation communications and storage. Besides, the new coupled and split-parity RS codes achieve low-latency/local failure recovery and accordingly enable the continued scaling of hyper-scale distributed storage and computing. This talk first reviews state-of-the-art VLSI implementation architectures for classic error-correcting RS and BCH decoders. Then the challenges and recent advancements on the implementation of the GII codes are discussed. The third part will focus on erasure-correcting decoding of the variations of RS codes for efficient failure recovery in distributed storage.