Due to the high cost of fabrication facilities, integrated circuits (ICs) are being designed and produced in a multi-vendor environment these days. Netlists of the ICs may be obtained from untrusted foundries or reverse engineering. Intellectual property (IP) piracy and counterfeiting cause severe economic loss to the IC designers. Various logic-locking schemes have been developed to protect IPs and prevent counterfeiting. The basic idea is to insert key-controlled logic components so that the chip does not function correctly without the right key, which is handled and distributed by the IC designer. On the other hand, many techniques have also been proposed to attack logic-locking schemes, including the powerful satisfiability (SAT)-based attack and its variations, removal attacks, and bypass attacks. Existing logic-locking designs that are better at resisting one type of attacks are often vulnerable to another. The first part of this talk discusses the generalization of the constraints needed to resist the SAT attack as well as the insights it provided to the understanding of existing designs and achievable tradeoffs on the resiliencies to various attacks. The generalization unifies many previous logiclocking schemes, such as the Anti-SAT, SARLock, and cascaded (CAS)-lock, under the same framework. Without sacrificing the SAT-attack resiliency, the logic-locking designs based on the generalized constraints can achieve higher corruptibility. They also allow a large variation of functions to be utilized and accordingly thwart any attacks based on functional analyses. Additionally, the constraints can be further relaxed in the striped functional logic-locking (SFLL) setting to resist removal attacks with lower complexity. The second part of this talk focuses on the new direction of logic locking utilizing algorithmic variations. Unlike logic-level methods as used in all previous designs, algorithmic-level schemes are very difficult to attack without detailed knowledge on the algorithms implemented in the ICs. Such schemes are essential to securing the design given the many available and ever-developing attacks for logic-level approaches. In particular, this talk will show that the large number of variations of finite field construction can be utilized to obfuscate a broad range of en/decryptors and error-correcting en/decoders that are used in numerous digital communication and storage systems, such as those for the Advanced Encryption Standard (AES), various light-weight cryptography, Reed-Solomon codes, and BCH codes. Additionally, existing logic-locking schemes only cause negligible loss on the performance of the systems that are self-correcting or fault-tolerating even if a wrong key is used. This talk will also discuss new algorithmic obfuscation schemes that significantly degrade the performance of the self-correcting lowdensity parity-check decoders, which are used in many digital communication systems and postquantum cryptography.