Details
Presenter(s)
![Gerson D Andrade Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/7317291.png?h=1e639c34&itok=NB7R0VUF)
Display Name
Gerson D Andrade
- Affiliation
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AffiliationUniversidade Católica de Pelotas (UCPel)
- Country
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CountryBrazil
Abstract
This paper compares three different FinFET full-adder topologies based on elementary logic gates regarding the delay and power aspects, considering a traditional design and a design under process, voltage, and temperature (PVT) variations. The delay suffers a deviation of at least 36%, 58%, and 58.5% with PVT variations. The impact on power is around 62.4% for all types of variability. As PVT variability is a crucial concern in nanotechnologies, we also evaluated a mitigation approach based on the addition of sleep transistors. We can obtain circuits up to 39.6% more reliable to the PVT influence with this strategy.