Details
Presenter(s)
Display Name
Edoardo Ragusa
- Affiliation
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AffiliationUniversity of Genoa
- Country
Abstract
This paper tackles the design of a pipelined digital architecture supporting the $n$-mode tensor-matrix product in the fixed-point representation. The solution balances throughput, area, and energy consumption. The design introduces a pipeline to reduce the latency when multiple input tensors should be processed. Experimental tests on Kintex-7 xc7k160tiffv676-2L FPGA confirm that the architecture leads to an efficient digital implementation, which can afford real-time performance on benchmark applications with power consumption lower than $\\mathbf{110 mW}$