Details
Presenter(s)
![Zhongkai Wang Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/12871_0.jpg?h=bdb2e6f8&itok=q1dwbHuD)
Display Name
Zhongkai Wang
- Affiliation
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AffiliationUniversity of California, Berkeley
- Country
Abstract
We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma (∆Σ) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 299.5 fs and power of 9.9 mW from a 1-V supply.