Details
Poster
Presenter(s)
![Siang-Sin Shan Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/18912.jpg?h=15ffb45d&itok=S3AfDPBP)
Display Name
Siang-Sin Shan
- Affiliation
-
AffiliationNational Chiao Tung University
- Country
Abstract
This paper proposes a low-power, high-linearity capacitive-sensing readout circuit with timing signal processing and a feedback loop. The timing subtraction and delay-line feedback help to improve the dynamic range of the readout circuits without increasing power consumption. This design achieves R2 linearity that is greater than 0.99 in a capacitor range of 20–90 pF and 5.6 µs/pF while only consuming 31µW. While implemented using digital circuits, the proposed design provides more flexibility over sensing element variations as well as scalability for advanced technology nodes.